The present invention relates to a data processing apparatus capable of processing both scalar and vector instructions.
The following two methods are conventionally reported as a method to be performed in a data processing apparatus of this type when a vector store instruction having no definitive data is output during instruction issuing performed in accordance with an instruction issuing order designated by a program:
(1) Issuing of the vector store instruction and subsequent instructions is delayed until data is determined.
(2) Of instructions subsequent to the vector store instruction, instructions which can pass are previously issued. After data of the vector store instruction is determined, the vector store instruction is issued as if it is issued in accordance with the instruction issuing order.
If a data processing apparatus of this type has a scalar cache memory which can be accessed by only a scalar instruction, processing according to a vector store instruction is performed only in a main memory. Therefore, if data corresponding to a store address of a vector store instruction is present in a scalar cache memory, the data is nullified to ensure data consistency. Note that nullification of data in the scalar cache memory is performed in units of blocks. This nullification processing of block data in the scalar cache memory is conventionally performed by activating nullification processing unit after a vector store instruction is issued so that the unit nullifies corresponding block data.
When a vector store instruction having no definitive data is output during instruction issuing performed in accordance with an instruction issuing order designated by a program, a processing speed of a data processing apparatus using the above method (1) is inevitably reduced. In a data processing apparatus using the method (2), a processing speed can be increased since instructions which can be passed are previously issued. If, however, the data processing apparatus using the method (2), although this is the same as the apparatus using the method (1), has a scalar cache memory which can be accessed by only a scalar instruction, nullification processing must be performed for the scalar cache memory in accordance with a vector store instruction. This nullification processing can be conventionally executed only after the vector store instruction is issued and therefore is an obstacle to a higher processing speed.